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Senior Analog Layout Engineer
Job Description & How to Apply Below
We are seeking a highly skilled Senior Layout Engineer to lead the physical implementation of critical analog and mixed-signal blocks. You will work closely with circuit designer to translate schematics into high performance, DRC/LVS-clean layouts for advanced process Nodes (e.g., 40nm, 22nm). This role demands deep knowledge of parasitic effects, matching, and isolation techniques.
Key Responsibilities- Execute full custom analog layout for blocks such as ADCs/DACs, PLLs, BG, LDOs, OPAMP, and Ser Des.
- Optimize layout for matching, minimal parasitic capacitors and resistors, and power/gnd distribution.
- Perform parasitic extraction, EM/IR analysis, and Reliability checks.
- Drive layout vs. schematic (LVS) and design rule check (DRC) closure.
- Collaborate with circuit designers to propose floor plans and resolve trade-offs.
- 5+ years of analog/mixed-signal layout experience.
- Proficiency in Cadence Virtuoso (Layout XL, XL/Calibre).
- Experience with advanced nodes (
Position Requirements
10+ Years
work experience
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