PCIe DV Engineer - SV/UVM; Gen
Listed on 2026-11-06
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Engineering
Test Engineer, Validation Engineer, Quality Engineering, Electronics Engineer
HCL Technologies Limited is seeking a Design Verification Engineer to join our semiconductor verification team in Canada. You will design and develop robust SV/UVM-based verification environments, verify PCIe Gen3/Gen4/Gen5 protocols, and contribute to reusable test benches and methodologies.
You should be proficient in SVA, coverage-driven verification, and constrained-random testing, with experience using simulators such as VCS, Xcelium, or Questa.
We are seeking a motivated PCIe DV Engineer - SV/UVM (Gen3-5) to join HCL Technologies Limited in Canada.
Are you ready to take on the PCIe DV Engineer - SV/UVM (Gen3-5) role at HCL Technologies Limited?
We would love to welcome a new PCIe DV Engineer - SV/UVM (Gen3-5) to our team in Canada.
For the PCIe DV Engineer - SV/UVM (Gen3-5) position at HCL Technologies Limited, we are reviewing applications now.
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