Senior Distinguished Engineer, SerDes Receiver & ADC

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $500M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical.

Our team is talent-dense andhigh-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard.

About the Role

We are building a world-class Ser Des engineering organization focused on next-generation, ultra-high-speed connectivity for AI data centers and high-performance computing.

We are seeking an exceptional technical leader to define and drive the architecture and implementation of next-generation Ser Des receiver front ends and high-speed analog-to-digital converters (ADCs), targeting ultra-high sampling rates in advanced process technologies at 5nm and below.

This is a high-impact technical leadership role for an engineer who combines deep expertise in high-speed analog and mixed-signal circuit design with strong architectural judgment and a proven ability to turn ambitious performance targets into silicon.

As a key technical leader, you will shape receiver architecture, drive critical circuit and system-level trade-offs, and work across analog design, DSP, clocking, digital implementation, and silicon validation to deliver industry-leading receiver performance. You will have the opportunity to influence the technical direction of our Ser Des platform and establish the foundation for future generations of high-speed connectivity.

Responsibilities:

• Receiver Architecture: Define and drive the architecture of next-generation, ultra-high-speed Ser Des receivers, including the analog front end, ADC, sampling architecture, clocking interfaces, and integration with digital signal processing.
• High-Speed ADC Development: Lead the design and optimization of ADCs targeting 100+ GS/s, addressing sampling speed, resolution, linearity, noise, power efficiency, and implementation complexity.
• Analog Front-End Design: Drive receiver front-end development, including high-bandwidth input stages, equalization, gain control, sampling networks, and other critical analog building blocks.
• Advanced-Node Implementation: Lead circuit design and implementation in 5nm and below technologies, leveraging advanced CMOS capabilities while managing device limitations, parasitics, variability, power integrity, and layout-dependent effects.
• System-Level Optimization: Establish architectural trade-offs across bandwidth, signal-to-noise ratio, effective number of bits (ENOB), jitter tolerance, power consumption, and DSP complexity to optimize overall link performance.
• Clocking and Sampling: Collaborate on clock generation and distribution, sampling-clock quality, aperture jitter, phase noise, and clock-to-data timing requirements at extreme sampling rates.
• Technical Leadership: Set technical direction, guide critical design decisions, mentor senior engineers, and drive resolution of complex circuit and system-level challenges.
• Cross-Functional Collaboration: Partner closely with TX, clocking, DSP, physical design, package, signal integrity, and silicon validation teams to deliver an integrated, high-performance Ser Des solution.
• Silicon Execution: Drive feasibility studies, architectural modeling, circuit simulations, design…