Hyperscale ASIC Performance Architect & Modeling Lead
Listed on 2026-11-04
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Design & Architecture
Engineering Design & Technologists -
Engineering
Engineering Design & Technologists, Hardware Engineer, Test Engineer
Meta's Silicon Engineering organization is building custom silicon solutions powering Meta's AI and data center workloads. You will define and drive architectural performance analysis, pre-silicon modeling, and microarchitectural exploration of custom ASICs for Meta's infrastructure.
The role requires 8+ years in ASIC design and 5+ years in performance modeling, with C++ and Python proficiency. Collaboration with architecture, RTL, and software teams is essential to meet throughput, latency, and
The Hyperscale ASIC Performance Architect & Modeling Lead role at Meta is now open for applications in Richmond, VA, United States.
Our group is growing, and we are hiring a Hyperscale ASIC Performance Architect & Modeling Lead in Richmond, VA, United States.
This opening is for the Hyperscale ASIC Performance Architect & Modeling Lead role at Meta.
We are seeking a motivated Hyperscale ASIC Performance Architect & Modeling Lead to join Meta in Richmond, VA, United States.
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