Senior ASIC Design Engineer ML & Networking Accel
Listed on 2026-10-17
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Engineering
Hardware Engineer
Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, video transcoding and network acceleration.
We seek experts with 8+ years in micro-architecture and RTL development, Verilog/System Verilog, and SoC design experience. The role emphasizes timing/power closure, synthesis and formal verification, with competitive pay and equity in a leading internet company.
Our organisation is growing, and we are hiring a Senior ASIC Design Engineer for ML & Networking Accel in Richmond, VA, United States.
Take a moment to read everything above and see whether this role is right for you.
This posting is for the Senior ASIC Design Engineer for ML & Networking Accel role at Meta, based in Richmond, VA, United States.
We are looking to fill the Senior ASIC Design Engineer for ML & Networking Accel position at Meta in Richmond, VA, United States.
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