Hyperscale ASIC Performance Architect & Modeling Lead
Listed on 2026-10-17
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Engineering
Systems Engineer, Hardware Engineer, Test Engineer, Engineering Design & Technologists
Meta's Silicon Engineering organization is building custom silicon solutions powering Meta's AI and data center workloads. You will define and drive architectural performance analysis, pre-silicon modeling, and microarchitectural exploration of custom ASICs for Meta's infrastructure.
The role requires 8+ years in ASIC design and 5+ years in performance modeling, with C++ and Python proficiency. Collaboration with architecture, RTL, and software teams is essential to meet throughput, latency, and
We invite applications for the Hyperscale ASIC Performance Architect & Modeling Lead position located in Richmond, VA, United States.
The advertised compensation is 178..
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
Learn more about the Hyperscale ASIC Performance Architect & Modeling Lead role in the description above.
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