Digital Verification Engineer

Position: Staff Digital Verification Engineer
A growing semiconductor company developing advanced processing solutions for next-generation applications across embedded systems, IoT, and high-performance computing is looking to expand the team with a Staff Digital Verification Engineer. In this role, you will take full ownership of verification architecture across complex SoC and subsystem designs.

As a Staff Digital Verification Engineer, you will be responsible for defining and driving verification architecture — not just working within an existing environment. This includes building scalable, reusable UVM-based verification frameworks from the ground up and setting the overall verification strategy.

This Staff Digital Verification Engineer role is ideal for someone who has previously led the development of verification environments and can make key architectural decisions, rather than purely contributing at an implementation level.

Key Experience

Strong UVM expertise, with proven ownership of verification architecture design for complex SoC or subsystem projects

Experience building verification environments from scratch, including defining structure, reuse, and methodology

Ability to design layered / hierarchical testbench architectures, not just integrate into existing ones

Strong debugging and root-cause analysis skills across RTL and simulation

Experience with coverage-driven verification, including defining coverage models and driving closure

Comfortable working in Linux environments, with scripting in bash and/or Python

Nice to Have

Embedded C experience, particularly for processor or core-level verification

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