Digital ASIC Design Engineer

Position: Staff Digital ASIC Design Engineer
A European semiconductor company working at the forefront of ultra-low-power AI hardware is looking for a Staff Digital ASIC Design Engineer to take technical ownership of CPU architecture and subsystem integration within their SoC platforms.

What you’ll be working on

Key responsibilities include:

Designing and architecting RISC-V CPU cores and associated micro-architectures

Converting high-level system requirements into detailed CPU and subsystem specifications

Developing, debugging and maintaining RTL in Verilog / System Verilog for CPU and related logic

Defining SoC-level integration of CPU cores, including interaction with memory, interconnect and peripheral

Supporting top-level SoC validation with particular attention to CPU operation

Owning front-end design activities such as synthesis, static timing analysis and equivalence checking

Contributing to software-hardware co-design and CPU bring-up activities

Assessing and integrating third-party CPU-related IP where appropriatee designs

Required experience:

Strong hands-on experience with CPU architecture and micro-architecture design

Practical experience working with RISC-V based CPU cores, including customisation or extension

Deep understanding of CPU pipelines, memory systems, caches, MMUs, interrupts and bus interfaces

Proven ability to write and debug complex RTL using Verilog / System Verilog

Solid knowledge of SoC architecture with a focus on CPU integration

Experience across front-end design flows, including synthesis, STA and formal checking

Comfortable working alongside verification teams and understanding CPU-centric verification strategies

Familiarity with standard on-chip interconnect protocols such as AXI or AHB

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