Senior Physical Design Engineer

A major US semiconductor manufacturer is looking for a Senior Physical Design Engineer to help establish and expand its in-house ASIC implementation team, supporting the development of cutting‑edge precision timing and mixed‑signal semiconductor products.

You will join a highly successful global engineering organisation responsible for the implementation and delivery of complex digital and mixed‑signal ASICs. This is a unique opportunity to play a key role in building physical design methodologies and flows from the ground up, working closely with RTL, analog, verification, and product engineering teams across the full RTL-to-GDSII flow.

The desired applicant for the role of Senior Physical Design Engineer will have strong backend implementation expertise, excellent timing closure knowledge, and experience developing robust physical design methodologies using Cadence tools. Experience across low‑power and mixed‑signal designs would be highly advantageous.

Requirements

Degree / Masters / Doctorate in Electronics, Microelectronics, Physics, Computer Engineering, or a related field

Strong industry experience delivering complex ASICs through successful tape‑out

Proven expertise across the full RTL-to-GDSII implementation flow

Floor planning, power planning, power grid design, place and route (PnR), clock tree synthesis (CTS), and physical verification

Advanced Static Timing Analysis (STA), timing closure, timing constraints, and ECO implementation

Experience with low‑power implementation methodologies and UPF

Strong understanding of signal integrity, power integrity, EM/IR analysis, and physical sign‑off

Experience developing, maintaining, or building Cadence‑based physical design flows and methodologies from scratch

Scripting and automation skills using Tcl, Python, Perl, or Shell scripting

Ability to work closely with front‑end, verification, and analog teams to achieve successful silicon delivery

Excellent salaries, benefits, stocks, bonus, and visa sponsorship are all available for the correctly qualified candidate.

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