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Sr. Engineer, Layout Design

Job in 2280, Rijswijk, South Holland, Netherlands
Listing for: Qabird
Full Time position
Listed on 2026-07-24
Job specializations:
  • Engineering
    Electronics Engineer, Systems Engineer, Hardware Engineer, Electrical Engineering
Salary/Wage Range or Industry Benchmark: 113844 - 148874 EUR Yearly EUR 113844.00 148874.00 YEAR
Job Description & How to Apply Below

About Si Time

SiTime is the Precision Timing company.

Timing is the heartbeat of all electronics, ensuring performance, resilience and scalability. For decades, quartz devices, non-silicon technology, have kept systems in sync, but they struggle in harsher, more demanding environments. MEMS-based Precision Timing delivers greater accuracy, smaller size and resilience. Today, MEMS timing powers over 400 applications, including high-growth ones in AI datacenters, automated driving, industrial and humanoid robots, wearables and IoT.

Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better reliability. With more than 4 billion devices shipped, SiTime is changing the timing industry. For more information, visit

Job Summary

The Sr. Layout Design Engineer will lead top-level chip-planning and perform block-level custom layouts for CMOS and BiCMOS circuits. The Engineer will review and coordinate work performed by offshore layout designers. Train junior layout engineers and offshore contractors. Contribute to developing standard layout methodologies and build processes to achieve high layout quality.

Responsibilities
  • Remote interfacing with local and global design and layout teams in multiple design centers across different time zones
  • Lead top-level chip-planning and perform functional-block-level, block-level, sub-block level, leaf cell, standard cell custom layouts for CMOS and BiCMOS circuits
  • Perform schematic-driven layout and design constraints
  • Design die-area efficient layouts per circuit designer requirements
  • Perform block or top-level layout designs
  • Perform floor-planning, power line planning, shielding, and device-matching layout
  • Verify layouts. Pass DRC, LVS, and ERC
  • Contribute to various chip-level routing and layout needs
  • Perform chip level integration, verifications, and tape-out
  • Support other projects as needed by management
  • Train junior layout engineers and offshore layout contractors
  • Contribute to develop common best practices and workflow across all sites
  • Build process and procedures to achieve high layout quality
Qualifications & Requirements
  • AA/AS Degree in Layout Design or related field or equivalent experience
  • 10 years of experience with layout design for analog and full-custom digital blocks
  • Experience with TSMC 180nm, 65nm, 22nm process technologies
  • Proficient in using layout editing tools in the Cadence Virtuoso design environment
  • Solid knowledge of debugging DRC/LVS/ERC with Cadence PVS or Mentor Calibre
  • Understanding of layout topics such as parasitic, matching, crosstalk, transistor layout dependent effects, latch-up, IR drop, electromigration, deep N-well and NTN isolation
  • Strong capability of solving device matching, electromigration, signal integrity and power distribution problems while meeting area constraints
  • Experience in chip-level floor planning and analog block integration
  • Experience with chip level integration, verifications, and tape-out
  • Desire to use productivity-enhancing tools and design scripts to automate tasks
  • Must be able to lift, push, and pull up to 5 lbs.
Desired Characteristics & Attributes
  • Attention to detail, organized, accurate and able to produce efficient layout techniques
  • Has a good track record of on-time work delivery
  • Self-motivated, team player with good communication skills
  • Ability to work well with others in a fast-paced collaborative team environment
Compensation Range

At SiTime, we believe great work deserves great rewards. We offer a comprehensive and highly competitive compensation package designed to attract top talent. In addition to base salary, this role is eligible for a quarterly bonus tied to the achievement of innovation goals. We also offer equity grants.

SiTime is an Equal Opportunity Employer. We treat each person fairly and do not tolerate discrimination or harassment against anyone on the basis of any protected characteristics. SiTime participates in the E-Verify program.

Learn More about Si Time

Review the Get to Know SiTime section of our career page to explore our culture, values, and what makes us unique.

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