Lead Physical Design Manager for SoC Tapeout & Flow

Job Title:
Technical Manager

Job Description s:Responsible for leading the entire APR implementation flow from netlist-to-GDS, including floorplan, place and route, CTS, STA, PDV/EMIR/Noise/SigEM cleanup and signoff on lower power SoC blocks. Additional responsibilities of the position, include:

Lead and work on multiple complex SoC/IP Physical Design projects for TSMC’s key customer, providing overall technical support for the team and focus on a block or partition for hands-on physical design work;
Coordinate project needs and priorities within the project team members, ensuring alignment of quality for customer support;
Physical Design work is focused on TSMC’s latest technology nodes for TSMC’s key customer’s product SoCs;
Current project is based on TSMC’s A14 technology node;
Complete entire physical implementation of block level and tape out production chip;
Provide technology specific design solutions tailored for the SoC/IP while working on the projects;
Block level floorplan with the ability to analyze the quality of the floorplan;
Customized Clock Tree structure and Place & Route;
Implement ECOs for timing closure;
Signal EM/Noise and Power IR/EM analysis and fix; DRC/LVS/ERC/ANTENNA analysis and cleanup;
Physical verification signoff to meet tape out quality;
Act as a mentor for junior and mid-level engineers and extend readiness for expanded responsibilities.

Requirements:Master’s degree or foreign equivalent in Electrical Engineering, Computer Engineering, or a related field of study, and two (2) years of experience in a related position.

Work experience or academic coursework must have included:
Experience with block-level execution of physical design process;
Experience managing Netlist-to-GDS flow for design outcomes;
Experience providing high-quality partition designs to meet customer requirements;
Experience implementing technology across projects driving improvements; and Experience maintaining quality control standards integrating technology.

Work site: TSMC Technology Inc., 2851 Junction Ave., San Jose, CA 95134 and various unanticipated work locations

Salary Range: $155,896 to $219,000/year.

Company Description

As a trusted technology and capacity provider, TSMC is driven by the desire to be:

• The world’s leading dedicated semiconductor foundry
• The technology leader with a strong reputation for manufacturing excellence
• Advancing semiconductor manufacturing innovations to enable the future of technology

TSMC pioneered the pure-play foundry business model when it was founded in 1987 and has been the world’s leading dedicated semiconductor foundry ever since. The Company supports a thriving ecosystem of global customers and partners with the industry’s leading process technologies and a portfolio of design enablement solutions to unleash innovation for the global semiconductor industry. With global operations spanning Asia, Europe, and North America, TSMC serves as a committed corporate citizen around the world.

In North America, TSMC has a strong sales and service organization that works with customers by helping them achieve silicon success with cutting-edge technologies and manufacturing excellence. The Company has continued to accelerate its R&D investment and staffing in recent years and is expanding its manufacturing footprint to support customer innovation with 3D IC technologies and optimal manufacturing capacity.

For positions requiring access to technical data subject to export control regulations, including Export Administration Regulations, TSMC North America may have to obtain export licensing approval from the U.S. Government for certain individuals. All employment is contingent upon TSMC North America obtaining any export license or other approval that may be…