Senior PCIe Subsystem RTL Architect
Listed on 2026-10-30
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Engineering
Systems Engineer, Test Engineer, Hardware Engineer
TYLsemi, Inc. is seeking a Principal PCIe Sub-system Front-end RTL lead to own the PCIe microarchitecture for high‑performance compute chiplets.
You will drive integration of PCIe IP, define lane configurations, and oversee TL pipelines, VC and flow‑control, while collaborating with firmware and physical design teams. You will mentor RTL engineers, define verification plans with DV teams, and engage with customers on interface bring‑up.
We are seeking a motivated Senior PCIe Subsystem RTL Architect to join TYLsemi in San Jose, CA, United States.
This opportunity is part of our work in Engineering.
The advertised compensation is 238..
This role offers the option to work remotely.
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
Learn more about the Senior PCIe Subsystem RTL Architect role in the description above.
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