Digital Design Engineer; Mid-Senior Level

Movandi has made a big impact on 5G in a short amount of time, from foundational research and innovative modular, high-efficiency mmWave system design to the introduction of our BeamXR 5G system that delivers measurable improvements in performance, coverage, and latency. Now more than ever, 5G — supported by Movandi technology — is becoming an integral part of the telecommunications landscape.

At Movandi we work as a team of sharp engineers who thrive on hard problems. If you want your work to have a direct impact on the future of 5G connectivity, this is the role for you.

We're looking for an experienced Digital Design Engineer to take ownership of complex digital subsystems within our hardware team. You'll lead RTL design and verification efforts for FPGA and ASIC targets, drive microarchitecture decisions, and serve as a technical reference for the broader team. You'll work closely with hardware, embedded software and verification engineers to ship robust, high-performance designs on time.

• RTL ownership: Architect and implement synthesizable RTL in VHDL or System Verilog for FPGA and ASIC targets, with a focus on performance, reusability, and long-term maintainability.
• Microarchitecture: Contribute to and lead block-level design decisions; pipelining strategy, clock domain partitioning, power/performance/area trade-offs, and document them clearly for design reviews.
• Verification leadership: Define and execute verification strategies using System Verilog and cocotb. Develop constrained-random test benches, close functional and code coverage, and triage simulation failures efficiently.
• Timing closure: Drive STA and timing constraint development (SDC/XDC), identify critical paths, and work with synthesis and P&R flows to close timing on complex, multi-clock designs.
• Lab bring-up & debug: Lead or actively participate in hardware validation. From JTAG bring-up and FPGA prototype debug through to silicon characterisation using oscilloscopes, logic analyzers, and custom test frameworks.
• Technical mentorship: Review the work of junior engineers, establish coding standards, and contribute to continuous improvement of team processes and tooling.
• Cross-functional collaboration: Interface with RF, analogue, and firmware teams to define interfaces, agree on integration strategies, and resolve system-level issues.

• Experience: 5–10 years of industry experience in digital IC or FPGA design, with a track record of shipping real silicon or production FPGA systems.
• HDL expertise: Strong, production-proven proficiency in System Verilog and/or VHDL, synthesizable RTL, parameterised design, and structured coding for reuse and review.
• Digital design depth: Expert-level understanding of synchronous design principles, multi-clock domain management, CDC strategies, reset topologies, metastability hardening, and pipeline design.
• Verification competence
• Timing & implementation: Working knowledge of STA, timing exceptions, false paths, and constraint authoring; experience with FPGA implementation flows or ASIC synthesis.
• Scripting & automation: Proficient in Python and/or Tcl for build automation, regressions, and flow scripting. Comfortable in a Linux-based development environment with Git.
• Communication: Able to produce thorough design specifications, lead design reviews, and communicate trade-offs clearly to both engineering and management stakeholders.

• Experience with high-speed serial interfaces (PCIe, Ethernet, DDR) or RF/mmWave digital back-end design.
• Familiarity with formal verification methods (model checking, equivalence checking).
• Exposure to ASIC physical design flows: place-and-route (Genus and Innovus), DRC/LVS, sign-off (Voltus, Tempus), ATPG test pattern generation (Modus).
• C/C++ for embedded co-development, firmware bring-up, or hardware/software interface definition.
• Experience mentoring junior engineers or leading small technical work streams.

• HDLs: System Verilog, VHDL, Verilog
• FPGA: Xilinx Vivado, Lattice Radiant; IP integrators and constraint management
• ASIC: Cadence Genus/Innovus
• Simulation/Verification: Cadence Xcelium, cocotb
• Workflow: Git, Jenkins, Python/Tcl, Linux shell, Jira/Git Hub