Hardware System Architect Lead, GPU Platform

We make the world's compute radically more efficient.

Think AI was founded in Riyadh in 2025 on one problem: expensive silicon sitting underused, held back by software blind to the hardware it runs on. We design and build the machine and the orchestration together, in one building, so that stops being true.

To redefine AI infrastructure from the silicon up.

To build the most efficient compute platform on earth, where hardware and software co-evolve to maximise intelligence. To ignite a new golden age of engineering, where anyone can own, operate, and scale frontier AI without compromise, without dependency, and without wasted compute.

Four principles run through everything we do. We look for these in how people demonstrate the values in their everyday work, not in how they talk about themselves.

You own the outcome, not just the task. You're frugal with resources and you put the mission ahead of your own comfort.

You move with velocity. You ship quickly and reiterate and once a decision is made, you disagree and commit.

You build for the customer. You think big and execute simply and you measure yourself on outcomes, not activity.

You go deep on the hard problem. Excellence is your default and you take real pride in delighting the customer.

This role owns the architecture of Think AI's multi-accelerator server platforms, the systems that sit underneath every node SKU in our product line and the ILM orchestration platform that runs on them. The first platform you will own is a high-density multi-accelerator system with true one-to-one GPU-to-NIC affinity that scales in accelerator count rather than stopping at a fixed number, built for a mixed-silicon fabric that runs NVIDIA, AMD, and Intel accelerators side by side.

You will take it from block diagram to manufacturing release in our Riyadh facility, and then set the platform direction for every node generation that follows.

Today we own the specification and work with a JDM partner on detailed board design; over time this role builds the in-house board design team that brings schematics and layout fully under our control. We want someone who has shipped dense multi-GPU platforms, argued over lane budgets and switch partitioning, and brought a system through EVT, DVT, and PVT into volume.

You also own platform quality: nothing leaves the Riyadh floor until it has been validated at board, server and rack level.

• Own the system architecture end to end: CPU platform selection, PCIe Gen5 and Gen6 topology, switch selection and partitioning, lane budgets, and GPU-to-NIC affinity across the full chassis.
• Design for GPUDirect RDMA and peer-to-peer traffic across heterogeneous accelerators, and validate ACS, ATS, IOMMU, and P2P behavior for each silicon vendor on the platform.
• Own the signal integrity strategy across retimers, MCIO and cabled PCIe, risers, backplanes, and channel loss budgets, working with layout and SI engineers through every board spin.
• Lead power and thermal architecture for dense, high-TDP accelerator configurations, covering CRPS power delivery, airflow, and liquid-cooling readiness, together with our mechanical and thermal engineers.
• Define BIOS/UEFI and BMC requirements, and work with the ILM software team on bring-up, telemetry, firmware, and fabric integration so the hardware and orchestration layers are designed as one system.
• Write the platform specification and reference design our JDM partner builds to, and own design reviews of every schematic, layout, and BOM before release.
• Select and manage ODM and JDM partners for motherboards, chassis, and PCIe switches, and drive each platform through EVT, DVT, and PVT into production at our Riyadh manufacturing facility.
• Lead the move from JDM to in-house board design, taking ownership of schematics, layout, and SI/PI one platform at a time while PCB fabrication and assembly stay with partners, and own the roadmap for future generations, including Gen6 switching, CXL, and rack-scale integration.
• Own the platform validation and quality strategy: validation plans, qualification matrices, and EVT, DVT, and PVT entry and exit criteria, covering PCIe link training and margining, memory qualification across DIMM vendors, accelerator and NIC interoperability, thermal, power, and long-duration stress testing.
• Drive Design for Test and Manufacturing (DFx) with our manufacturing team so every node can be tested at board, server, and rack level, including factory test coverage, burn-in, and…