Design Verification Engineer – IP

HCLTech is looking for a highly talented and self-motivated Design Verification Engineer - IP to join it in advancing the technological world through innovation and creativity.

Job

Position Type:
Full Time

Location:
Remote

We are looking for an experienced Design Verification Engineer responsible for IP verification
, including development of reusable verification environments, execution of verification plans, RTL debugging, regression analysis, and functional/code coverage closure.

The ideal candidate will have strong hands‑on experience with System Verilog, UVM, RAL modeling, assertions, coverage-driven verification, and RTL/IP verification
.

• Develop and enhance reusable System Verilog/UVM-based verification environments, including test benches, agents, monitors, drivers, scoreboards, sequences, and assertions.
• Develop and execute comprehensive verification plans, test cases, and functional coverage models.
• Create and execute directed and constrained-random test scenarios for IP/Block-level verification.
• Integrate, configure, and debug UVCs/VIPs within the verification environment.
• Drive functional coverage and code coverage closure, including identification and analysis of coverage gaps.
• Verify RTL functionality of IP blocks, including FSMs, DAC control logic, and pattern memory/controller modules.
• Perform RAL modeling and RAL-based register verification, including register access, prediction, mirroring, and coverage.
• Debug RTL, protocol, testbench, simulation, and verification environment issues.
• Perform regression analysis and support verification sign-off activities.
• Support low‑power verification and Gate-Level Simulation (GLS) debugging as required.
• Collaborate closely with RTL design and SoC teams to deliver high‑quality, reusable verification environments and collateral.

• Strong programming experience in System Verilog and UVM
  .
• Hands‑on experience with IP Verification and verification environment development.
• Strong understanding of digital design fundamentals, RTL, FSM architectures, and verification methodologies.
• Strong hands‑on experience with UVM RAL / Register Abstraction Layer modeling and verification.
• Experience with register access, prediction, mirroring, register coverage, and RAL-based verification sequences.
• Experience with directed testing and constrained‑random verification.
• Experience with functional coverage, code coverage, assertions, and coverage closure.
• Experience integrating and debugging UVCs/VIPs.
• Strong experience with RTL and protocol debugging.
• Experience with regression execution, failure analysis, and debugging.
• Familiarity with low‑power verification concepts and GLS debug.
• Strong analytical, debugging, and problem‑solving skills.
• Ability to work effectively with Design, Verification, and SoC engineering teams.

Pay Range Minimum: $95000/Year

Pay Range Maximum: $192000/Year

HCLTech is an equal opportunity employer, committed to providing equal employment opportunities to all applicants and employees regardless of race, religion, sex, color, age, national origin, pregnancy, sexual orientation, physical disability or genetic information, military or veteran status, or any other protected classification, in accordance with federal, state, and/or local law. Should any applicant have concerns about discrimination in the hiring process, they should provide a detailed report of those concerns to  for investigation.

A candidate’s pay within the range will depend on their skills, experience, education, and other factors permitted by law. This role may also be eligible for performance-based bonuses subject to company policies. In addition, this role is eligible for the following benefits subject to company policies: medical, dental,…