VLSI Design Engineer: DRC/LVS, Timing & ECOs
Listed on 2026-11-05
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Engineering
Systems Engineer, Engineering Design & Technologists, Electronics Engineer
TSMC Technology, Inc. in San Jose, CA seeks a Design Engineer to perform DRC/LVS/ANTENNA analysis, fix violations, and support timing closure for high-performance blocks. The role involves clock tree customization, ECOs, floor planning, and thorough documentation of methodologies.
You will work on power/EM analysis, signal integrity checks, and signoff tasks while sharing best practices with the team to improve overall efficiency and collaboration.
This role, VLSI Design Engineer: DRC/LVS, Timing & ECOs at TSMC, could be your next career step.
Step into the VLSI Design Engineer: DRC/LVS, Timing & ECOs role at TSMC in CA, United States and grow with us.
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The position is based in CA, United States.
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