Principal Verification Architect - Lead Strategy & UVM Labs

A technology company in the semiconductor industry is seeking an experienced Principal Verification Engineer to lead the definition of verification strategies and develop advanced test environments. This role involves collaborating globally to ensure product designs meet high-performance standards. The ideal candidate will possess extensive experience in verification, a strong knowledge of System Verilog, and proficiency in UVM methodology. The position offers a full-time contract with a competitive salary range of $150,000 to $200,000 per year.
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