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Fpga Design Engineer

Job in Salem, Marion County, Oregon, 97308, USA
Listing for: Actalent
Full Time position
Listed on 2026-10-20
Job specializations:
  • Engineering
    Electronics Engineer, Hardware Engineer, Systems Engineer
Salary/Wage Range or Industry Benchmark: 110000 - 172000 USD Yearly USD 110000.00 172000.00 YEAR
Job Description & How to Apply Below
Job Title:

FPGA Design Engineer (Senior-Level Digital Design)

Job Description

This Senior-level FPGA Design Engineer role focuses on full life-cycle digital product development for aerospace, defense, SATCOM, and infrared systems. You will translate complex system requirements into robust digital hardware and FPGA implementations, working with cutting-edge technologies from major FPGA vendors to support high-speed interfaces, RF digital signal processing, embedded processing, and processor interfaces. The position is ideal for a well-tenured engineer who enjoys solving difficult problems, leading technical efforts with minimal guidance, and contributing to mission-critical systems for defense applications.

Responsibilities
  • Lead full life-cycle digital product development from system concept and requirements through design, implementation, verification, production, and field support.

  • Translate system performance and operational requirements into detailed embedded system requirements, digital design specifications, and test specifications.

  • Design, implement, and verify digital hardware circuits and FPGA-based subsystems using modern FPGA technologies from major vendors, including Xilinx and Intel (Altera).

  • Perform digital hardware circuit design, including simulation, schematic capture, test, integration, and troubleshooting.

  • Develop, code, and verify FPGA designs using HDL (VHDL and/or Verilog), ensuring robust functionality and performance.

  • Create and maintain test benches for functional verification using tools such as Mentor Graphics Questa Sim, ensuring thorough coverage and validation.

  • Drive synthesis, static timing closure, physical implementation, and FPGA image generation using tools such as Xilinx Vivado and Synopsys Synplify Pro.

  • Implement real-time digital signal processing (DSP) algorithms within FPGAs, using provided algorithms and specifications to achieve bit-exact behavior.

  • Apply high-speed digital design techniques, including pipelining, asynchronous clock domain management, synchronization, finite state machine design, multi-cycling, and FIFO usage.

  • Read, interpret, and create Interface Control Documents (ICDs) to ensure accurate and reliable system and subsystem integration.

  • Use documentation and revision control practices to manage design artifacts, code, and configuration baselines.

  • Collaborate closely with another team lead and cross-functional teams to coordinate design activities, resolve technical issues, and support program objectives.

  • Provide technical leadership and mentoring to other engineers, sharing best practices and guiding less-experienced team members.

  • Communicate effectively with stakeholders at all levels, including internal teams and external partners, to present design approaches, trade studies, and technical decisions.

  • Support integration and test activities in lab or field environments, including debugging and resolving complex digital and FPGA-related issues.

  • Contribute to projects supporting sustainment and enhancement of advanced aircraft systems and related electronic warfare and defense applications.

Essential Skills
  • Bachelors degree in Electrical Engineering, Computer Engineering, or a similar engineering discipline.

  • Minimum 9 years of digital electronics design experience with a bachelors degree, or minimum 7 years of digital electronics design experience with a masters degree in a technical field.

  • Extensive experience in digital hardware circuit design, including simulation, schematic capture, test, and integration.

  • Strong experience with HDL design using VHDL and/or Verilog.

  • Thorough understanding of synthesis, static timing closure, physical implementation, and FPGA image generation.

  • Demonstrated ability to create strong test benches and perform…

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