Job Description & How to Apply Below
My client develops ICs for a range of industrial and sensing applications. The Senior Layout Engineer will play an important role in taking mixed signal designs from initial layout through physical verification and tapeout.
The role
The Senior Layout Engineer will be responsible for:
Leading block and chip level layout and floor planning
Working closely with analog designers on layout topology, constraints and optimisation
Managing physical verification and supporting tapeout activities
Contributing to successful silicon releases across multiple projects
Supporting CAD tools, PDKs and design rule verification
Improving layout processes and methodologies
Providing technical guidance and mentoring to other engineers
Working with internal teams and external suppliers where required
The Senior Layout Engineer role would suit someone who enjoys working closely with analog design teams and wants to take ownership of technically challenging layout projects within an established semiconductor environment.
Visa sponsorship is unfortunately not available for this position, and the role requires the successful candidate to work full-time on site.
Please contact Parm Shergill for more information.
Position Requirements
10+ Years
work experience
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