Senior FPGA Design Engineer

Job Title: Senior FPGA Design Engineer

Reporting To: Engineer, Sr. Staff

Work Schedule: Hybrid - Torrance, CA

Moog is looking for a Sr. FPGA / Digital Design Engineer to develop high speed digital circuit designs and FPGAs for flight control and weapons bay actuators for next generation aircraft. You will solve challenging problems and develop solutions that find application across military aerospace industries. Reporting to an Engineering Manager, you will have a 9/80 work schedule and hybrid work options (3 days/week in the office).

This role can be located in either Torrance, CA or Salt Lake City, UT.

Moog's Military Aircraft Group is a global leader in designing primary and secondary flight control actuation systems (FCAS) for military aircraft. We design and integrate FCAS systems for cutting edge aircraft like the F-35 Lightning II and the V280 Valor next generation tiltrotor Aircraft. Headquartered in East Aurora, NY, Moog employs 14,000 employees in 24 countries. Working with us can mean deeper job satisfaction, better rewards, and a great quality of life, inside and outside of work.

• Contribute to the development of new electronic product requirements through consulting with our customers and system engineers
• Perform trade studies and analyses to validate conceptual designs
• Perform high speed digital circuit design including schematic capture and specifying printed circuit board design requirements (placement constraints, trace parameters, and routing layer constraints).
• Develop firmware for FPGAs that work with electronics, sensors, electro-hydraulic actuators, electromechanical components, and communication links for actuation systems or avionics equipment
• Conduct prototype testing, integration testing, and design verification and validation testing
• Document design, analysis, and verification results with accurate and concise reports
• Provide formal technical presentations to internal and external customers to support program review and business development
• Specify and support design of lab test setups

• Bachelor's Degree in Electrical Engineering
• 7+ years of professional work experience in design and development engineering
• 5+ years of digital design expertise including modern microprocessors / DSPs, high speed digital logic, FPGA, memory, analog-to-digital, digital-to-analog converters, and communication links
• Knowledge of board design and layout including design tools
• 5+ years of experience with VHDL or Verilog coding
• Experience designing test benches and simulations using digital simulation tools (example Questa, Active-HDL) for verification of FPGA designs
• Analysis expertise including power dissipation, power use, timing, signal integrity, component derating, and Acceptance Test / Built-In Test coverage

This position requires access to United States export-controlled information.

• Aerospace or Defense industry experience is desirable
• Experience developing design in accordance with DO-254
• Expertise with Hyper Lynx to analyze signal integrity
• 5+ years of experience with VHDL coding is desirable
• Experience with Allegro Capture and Allegro PCB

• Financial Rewards: competitive compensation package, annual profit sharing, matching 401k and the ability to participate in Employee Stock Purchase Plan, Flexible Spending and Health Savings Accounts
• Work/Life Balance:
  Flexible paid time off, holidays and parental leave program, relocation assistance
• Health & Welfare:
  Comprehensive insurance coverage including medical, dental, vision, life, disability, Employee Assistance Plan ("EAP") and other supplemental benefit coverages
• Professional Skills Development:
  Tuition Assistance, mentorship and coaching opportunities, leadership development and other personal growth programs
• Collaborative and Welcoming Workplace:
  Inclusive culture rooted in our values, enhanced by Employee Resource Groups, and team-building activities.
• Our Torrance and Salt Lake City sites have a 9/80 work schedule option for exempt employees (every other Friday off).

#LI-ML1