Principal DFT Engineer — ASIC/SoC Test Architect
Listed on 2026-10-30
-
Engineering
Test Engineer, Hardware Engineer, Systems Engineer, Electronics Engineer
Celero Communications, Inc. is seeking a Principal DFT Engineer to lead DFT efforts for ASIC/SoC designs in Irvine, CA.
You will architect and implement DFT solutions, drive signoff, and collaborate with RTL, verification, and physical teams to ensure robust testability. You will develop scan, ATPG, and MBIST strategies, validate fault coverage, and support manufacturing test readiness while contributing to silicon bring-up and yield improvements.
The Principal DFT Engineer — ASIC/SoC Test Architect role at Celero Communications, Inc. is now open for applications in United States.
Are you ready to take on the Principal DFT Engineer — ASIC/SoC Test Architect role at Celero Communications, Inc.?
We would love to welcome a new Principal DFT Engineer — ASIC/SoC Test Architect to our organisation in United States.
For the Principal DFT Engineer — ASIC/SoC Test Architect position at Celero Communications, Inc., we are reviewing applications now.
(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).