Senior Staff Engineer, NPI Packaging R&D

Location

San Diego, CA, US

pSemi Corporation is a Murata company driving semiconductor integration. pSemi builds on Peregrine Semiconductor’s 30‑year legacy of technology advancements and strong IP portfolio but with a new mission—to enhance Murata’s world‑class capabilities with high‑performance semiconductors. With a strong foundation in RF integration, pSemi’s product portfolio now spans power management, connected sensors, optical transceivers, antenna tuning and RF frontends. These intelligent and efficient semiconductors enable advanced modules for smartphones, base stations, personal computers, electric vehicles, data centers, IoT devices and healthcare.

From headquarters in San Diego and offices around the world, pSemi’s team explores new ways to make electronics for the connected world smaller, thinner, faster and better.

We are seeking an experienced Senior Staff Engineer to lead pSemi’s internal prototyping assembly laboratory. The laboratory operates in a very high‑mix low‑volume environment and supports the assembly of R&D prototypes, reliability test samples and engineering samples shipped to customers for testing. The role requires expertise in the assembly processes required for fully packaged, single die flip‑chip LGA, multi‑chip modules (MCM) and System‑in‑Package devices.

Assembly processing includes paste / flux screen printing for SMT components, SMT pick‑and‑place, flip‑chip attach, mass re‑flow, underfill dispense, potting or encapsulation via dam & fill, laser marking and package singulation. The ideal candidate will have extensive hands‑on experience with automated semiconductor assembly equipment such as paste / flux printers, SMT pick‑and‑place, plasma clean, underfill / potting compound dispensers, plasma cleaner, laser markers and saw singulation equipment.

The candidate should also be knowledgeable of the different semiconductor industry standards based on IPC, JEDEC, MIL spec, EIA and SMTA, as well as expertise in product qualification, process development, and team leadership. In addition, the candidate should be aware of developments in assembly and packaging technologies like WLFO, CoWos, etc.

• Cross‑Functional Leadership:
  Guide cross‑functional teams in making critical packaging mechanical decisions throughout the product development stages.
• Process Development & Risk Mitigation:
  Define and develop manufacturing processes by performing detailed design analysis (tolerance analysis, RMS, FMEA, etc.) and guiding risk assessments.
• Design Documentation & Oversight:
  Coordinate preparation of design documentation, BOM, and assembly process flows, ensuring all aspects meet technical specifications and quality standards.
• Team Mentorship:
  Mentor junior engineers and lead technical development efforts across packaging and assembly disciplines.
• Failure Analysis & Problem Resolution:
  Root cause analysis and resolution of issues during both the development and production phases.

• Education:
  
  Bachelor’s degree in Engineering (Mechanical, Electrical, Packaging, Materials, or Chemical), Physics, or Chemistry. MS preferred.
• Experience:
  
  At least 12 years in electronics packaging, including 5 years of hands‑on experience in the assembly of LGA, MCM and SiP‑specific assembly processes and packaging‑related technologies.
• Document Management systems: experience working with document management systems, e.g. Agile, the ECO process and Product Life Cycle management.
• Process Documentation:
  Ability to document the assembly process flow via standard process descriptions, detailed work instructions, quality specifications based on JEDEC & MIL standards.
• Design & Development Tools:
  Proficient with design tools such as AutoCAD, Cadence Allegro, CAM
  350 or similar. Hands‑on experience with Solidworks for basic 3D model generation.
• Experience setting up and overseeing operation of a semiconductor proto‑assembly lab for quick‑turn customer sampling.
• Packaging Knowledge:
  In‑depth understanding of microelectronic packaging technologies, including flip‑chip bumping, wafer backend processing and SMT.
• Cross‑Functional…