ASIC Timing and Methodology Engineer

Company:

Qualcomm Technologies, Inc.

Job Area:

Engineering Group, Engineering Group > ASICS Engineering
General

Summary:

As a Timing Engineer, you will play a vital role in Timing analysis targeting the Mobile, Compute, Automotive and IOT markets

• The candidate will work with best-in-class methodologies, tools and technology to design innovative SOC products at the block/IP-level and at system-level in 5nm, 4nm and beyond (process technologies).

• You will be working with physical design team (and other teams) on timing closure, CAD teams, IP teams and Design Technology Teams for flow scripts/tools development and validation.

• Responsible for Spice simulations (Hspice/Finesim/AFS/Spectre/Infinisim) for PVT corners validation and STA vs spice correlation. Timing package validation across advanced process technologies using PT/PT-SI and Tempus.

• You will facilitate and drive STA methodology for Qualcomm using PT-SI, Tempus and best in class timing ECO tools . Work on timing sign off specification for different projects and support timing sign off for complex SOC’s. Hands on contribution for STA timing sign off.

• A timing Engineer should be able to understand all kind of intricate timing paths (digital, analog, mixed signal), timing constraints and provide solutions if required. Good understanding of RTL to GDS digital flow. Knowledge of DC/DCT/DCG/Genus/Oasis, ICC2/Fusion/Innovus/Aprisa, Red Hawk/Sea Hawk/Voltus is a plus.

• You should have good execution knowledge.

• Your contribution should improve timing convergence process across the company, design PPA, yield and support new advanced process technologies bring-up from pdk to vlsi design production.

• You should have good programming skills Python, Perl, TCL, Unix shell , C/C++.

• ML modeling experience is a plus

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
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EEO

Employer:

Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

Pay range and Other Compensation & Benefits:

$ - $
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation  also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus).

In addition, our highly competitive benefits package is designed to support your success at work, at home, and r recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at thislink.

If you would like more information about this role, please contact Qualcomm Careers.

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