Principal Fuse​/JTAG Design Lead

Principal Fuse/JTAG Design Lead at Arm

Our Solution Engineering division develops SoCs for various application segments, using the latest IP products from Arm and other vendors. We are looking for a creative and hard‑working SoC Lead Design Engineer to lead the team responsible for the development of the JTAG and Fuse Subsystems. The successful candidate will own the Microarchitectural Specifications, lead other designers and partner with the verification lead/team across multiple process nodes and product families.

You will join a team of dedicated engineers, collaborating with multiple other groups inside of Arm to design scalable and reusable Debug Control and Access IPs.

• Leading an IP development team which owns our reconfigurable Fuse and JTAG Subsystems.
• Working with the Architect(s) to understand Subsystem requirements, and developing design specifications that meet the quality, reliability, manufacturing and reconfigurable needs across multiple SoCs.
• Crafting design micro‑architecture specifications, developing the RTL, fixing bugs, running design checks and contributing to implementation constraints.
• Providing technical guidance and mentorship to the design team, engaging with partner teams for collaborative improvements in tools, technologies, methodologies and capabilities.
• Partnering with the verification lead to review test plans, debug design issues and crafting UVM components for IP and SoC integration of the Subsystems.
• Driving unification and efficient methods, as well as new methodologies used by the team.
• Acting as the 1‑Arm to ensure the best solutions are what Arm uses.
• Working with Project Management to define plans and execute schedules flawlessly.

• Degree in Computer Science, Electrical/Computer Engineering or a related field.
• 15+ years’ experience in designing complex subsystems or SoCs, including digital hardware design using System Verilog.
• Experience with analog hard IP integration, timing diagrams, BMODs and reconfigurable IP / Subsystem design.
• Experience with power and clock domain crossing, static design checks such as linting, CDC/RDC, X‑propagation.
• Experience with all stages of design: initial concept, specification, implementation, testing, documentation and support.
• Experience collaborating with the verification team on design quality closure.
• Experience with Perl, Python or other scripting languages.
• Leadership, mentoring or coaching experience.

• Experience with ARM-based designs and/or ARM System Architectures.
• Experience developing designs for OTP/Fuse usage models and JTAG/TAP protocols.
• Experience with SoC system use cases and debug methodologies.
• Experience developing and integrating subsystems for PCIe, UCIe, DDR/LPDDR/HBM, Ethernet, etc.
• Experience with DFT use cases and methodologies: RTL testability, scan insertion, OCC.

• Partner and customer focus
• Teamwork and communication
• Creativity and innovation
• Team and personal development
• Impact and influence
• Deliver on your promises

$241,100–$326,100 per year

At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email  All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation.

Arm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. The flexibility we can offer is limited by local legal, regulatory, tax, or other considerations; where this is the case, we will collaborate with you to find the best solution.

Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization and do not discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.

• Seniority level:
  Mid‑Senior level
• Employment type:
  
  Full‑time
• Job function:
  Design, Art/Creative, and Information Technology
• Industries:
  Semiconductor Manufacturing, Software Development, and Computer Hardware Manufacturing