Analog Intern: DDR PMIC Research & Cadence Design
Listed on 2026-10-08
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Engineering
Electronics Engineer, Systems Engineer
Renesas MID (Memory Interface Division) seeks an Analog Intern to contribute to the development of the next generation DDR PMIC in a multi-site internship (San Jose, San Diego, or Plano).
You will research PMIC control architectures, perform simulations at various levels, and build circuits using Cadence, supported by DE and AE engineers. A strong background in power electronics and analog design is required, with ongoing graduate studies through 2027.
We would love to welcome a new Analog Intern: DDR PMIC Research & Cadence Design to our organisation in San Diego, CA, United States.
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
Learn more about the Analog Intern: DDR PMIC Research & Cadence Design role in the description above.
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