SoC Power Design Engineer - Low-Power RTL and UPF

Qualcomm Technologies, Inc. seeks an ASIC Engineer focused on low-power design across SoC levels. You will work with frontend RTL, DFT, Synthesis, and Physical Design to implement and validate power intent (UPF) and related power models, contributing to power projections and clock/power analyses.

The role involves cross-functional collaboration with IP teams and CAD vendors to enhance power flows and ensure designs meet stringent low-power requirements across pre-silicon to post-silicon stages.

We invite applications for the SoC Power Design Engineer
- Low-Power RTL and UPF position located in San Diego, CA, United States.

Join QUALCOMM, Inc. and contribute to our ongoing work.

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This posting is for the SoC Power Design Engineer
- Low-Power RTL and UPF role at QUALCOMM, Inc., based in San Diego, CA, United States.