Gen, -Speed, Memory and Cache Controller Design Engineer

Qualcomm Technologies, Inc.

Engineering Group, Engineering Group > ASICS Engineering

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products.

Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.

• Bachelor's degree in Science, Engineering, or related field.

Next Generation, High-Speed, Memory and Cache Controller Design Team is looking for a Senior ASIC Design Engineers for the next generation high speed HBM/LPDDR/DDR memory controller. The front end of the DDR controller interfaces to the rest of the system such as CPU, GPU, DSP, Multimedia Processors and the engineer is expected to be responsible for enabling high speed (1

Ghz+) designs in QCT products.

The candidate will work on architecture, design (RTL coding), and deployment of the next generation, high-speed memory systems into QCT products. You will develop or contribute to the development of architecture and design specifications and drive the micro-architecture of portions of the logic design. You will implement and deliver RTL and work with verification engineers to deliver high quality designs. You will be responsible for debugging your designs and also provide debug support when integrated into the rest of the chip.

Synthesis, Timing Closure, Physical Design Support, Gate Level Simulations, Power Analysis are expected to be key tasks. You will make regular contributions to the overall improvement in design methodology to drive productivity and quality of results.

• Bachelor's or Masters degree in Science, Engineering, or related field.
• The team welcomes applications from recent graduates as well as early-career professionals with 3+ years of experience.

• LPDDR memory and cache controller, NoC based architectures especially the front end interfacing to the CPU, DSP, and multimedia processors
• Exposure to HBM memory type designs
• On-chip tightly coupled SRAM & L3 cache controller architecture/design
• Experience with x86 or ARM CPU/bus architectures
• Ordering of memory transactions and methods to enforce proper ordering in order to conform to ISA architecture specification

Required:

Master's, Computer Engineering and/or Electrical Engineering

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disabili or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process.

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EEO

Employer:

Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

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