Gen System Cache RTL Design Engineer
Listed on 2026-10-13
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Engineering
Systems Engineer, Electronics Engineer, Test Engineer, Hardware Engineer
Qualcomm Technologies, Inc. in San Diego seeks an ASIC Engineer to define, model, design RTL for SOC interconnects and memory subsystems, and optimize power and performance. The role includes collaboration across teams to ensure high-quality IP for Snapdragon platforms.
You will verify and debug designs through full project cycles, work to reduce silicon cost, and contribute to low-power, high-performance solutions in a fast-paced, innovative environment.
Our organisation is growing, and we are hiring a Next-Gen System Cache RTL Design Engineer in San Diego, CA, United States.
The position is based in San Diego, CA, United States.
This opportunity is part of our work in IT & Technology, Engineering.
The advertised compensation is 122..
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
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