ASIC​/RTL Design Engineer -speed Interfaces

Qualcomm Technologies, Inc.

Engineering Group, Engineering Group > ASICS Engineering

The Mixed-Signal IP team at Qualcomm is seeking skilled micro architect and digital design engineers to contribute to the development of next-generation, high-performance, low-power interface IPs - including Ser Des, DDR, and die-to-die interconnects - for integration across Qualcomm's product portfolio, including mobile, compute, data center, and AI. In this role, you will collaborate with a cross-functional team to architect, design, implement, and validate complex IP blocks.

Your work will directly support multiple business units and require a strong grasp of the full ASIC design flow, from RTL through GDSII, along with an understanding of the challenges associated with advanced semiconductor technologies.

• Architect and define the digital design of high-speed interface IPs (e.g., Ser Des, DDR, die-to-die) in close collaboration with system architecture and analog design teams
• Develop micro-architecture and implement RTL for complex mixed-signal IP blocks
• Apply advanced techniques in computer architecture, digital signal processing, and ASIC design to enhance power, performance, and area (PPA)
• Utilize industry-standard ASIC design tools for lint checking, clock domain crossing (CDC) analysis, design-for-test (DFT), synthesis, formal verification (FV), and static timing analysis (STA)
• Design and analyze DFT logic, including ATPG for stuck-at fault (SAF) and transition delay fault (TDF) coverage
• Create comprehensive design documentation, including hardware specifications
• Collaborate with the design verification (DV) team to define test plan, verify the design, and fix bugs
• Work with the physical design (PD) team to support floor planning, placement, and timing closure of IPs
• Support SoC integration and debug, including pre-silicon simulation and post-silicon bring-up

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

OR

Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.

OR

PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

• Master’s degree in Electrical Engineering, Computer Engineering, or a related field
• 7+ years of experience in RTL and ASIC design
• 5+ years of hands-on experience in micro-architecture and digital design for mixed-signal IPs such as Ser Des (PCIe, USB, UFS, MIPI), DDR PHY, PLLs, DACs, ADCs, and sensors
• Proficiency with industry-standard front-end ASIC design tools including VCS, Fusion Compiler, Prime Time, Power Compiler (PTPX), DFT Compiler, Spyglass, and others

• Ph.D. in Electrical Engineering with 5+ years of industry experience in high-speed digital circuit design
• Strong background in low-power digital design techniques
• Expertise in computer architecture, digital signal processing, and algorithm development
• Experience developing automation scripts and design productivity tools using Python or Perl

$ - $

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation  also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus).

In addition, our highly competitive benefits package is…