Senior ASIC/SoC Verification Engineer; SystemVerilog & UVM
Listed on 2026-10-15
-
Engineering
Test Engineer
Technical-Link N. America is seeking a Senior ASIC Verification Engineer with 8+ years of hands-on System Verilog and UVM experience to drive verification across IP, block, subsystem, and SoC levels. Satellite or DSP background is a plus but not required, and complex design debugging is essential.
The role emphasizes testbench development, scoreboards, reference models, and protocol monitors to ensure robust verification and signoff across multiple projects.
For the Senior ASIC/SoC Verification Engineer (System Verilog & UVM) position at Technical-Link N. America, we are reviewing applications now.
If your experience matches this role, we encourage you to apply.
All applications are reviewed carefully by our team.
The position is based in San Diego, CA, United States.
This opportunity is part of our work in Engineering.
The advertised compensation is 120..
(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).