Digital Design Engineer ASICS Engineering Posted

## Digital Design Engineer San Diego, California, United States of America Apply Now Find out how well you match with this jobJob :
3092707##
** Company:
** Qualcomm Technologies, Inc.##
** Job Area:
** Engineering Group, Engineering Group  ASICS Engineering
** General

Summary:

** Qualcomm’s high speed parallel interfaces team is looking for a motivated and driven ASIC front end design engineer to work with a world class global team tasked to architect, design, and implement industry leading DDR and die-2-die interfaces fueling the company’s growth in high-speed compute, and server domains.

The Digital Design Engineer will be responsible for designing, developing RTL, and implementing digital IPs serving the systems that connect SoC to DRAM devices and provide reliable high-speed link in multi-die systems. In this existing role you will work closely with systems architecture, verification, timing, and physical design engineers to design and implement control and data-path blocks for SoC interfaces. Ideal candidate will have experience on high speed, low power digital logic design development with hands on experience on ASIC front end implementation tool flow methodologies and silicon bring up.

Expertise required on digital IP design using System Verilog, logic synthesis, linting checks, clock domain crossing best practices and analysis, low power implementation and sign off, and gate level simulation debug.

Position requires working closely with cross functional teams to enable all phases of implementation and Si bring up. Prior experience with high-speed parallel physical interfaces designs and low power designs is a plus.
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* Minimum Qualifications:

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* • Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR  Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR  PhD in Science, Engineering, or related field.
** Required for this Role:*
* · Bachelor’s Degree in Science, Engineering, or related field.
· Minimum 4 years ASIC design, verification, or related work experience.
*
* Preferred Qualifications:

*
* · BS with 4 years or MS with 2 years relevant work experience
· Ideal candidate will have experience on high speed, low power digital logic design with hands on experience on ASIC front end implementation tool flows and silicon bring up.
· Expertise required on digital IP design using System Verilog, logic synthesis, linting checks, clock domain crossing best practices and analysis, low power implementation and sign off, design for test (DFT) flows for stuck and TDF modes, gate level simulation bring up and debug.
· Position requires working closely with cross functional teams in high paced and dynamic environment to enable all phases of implementation and Si bring up.
· Prior experience with high-speed parallel physical interfaces designs and low power designs is a plus.

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disabili or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process.

Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume…