Senior SV Verification Engineer; UVM/C++
Listed on 2026-10-31
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Engineering
Test Engineer, Electronics Engineer
Arrow Electronics, through its eInfochips division, is seeking a Design Verification Engineer in San Jose, CA. The role requires 6+ years of System Verilog HVL and C/C++, with strong UVM experience and C++ test benches. Travel to Arrow client sites may be involved as needed.
The candidate will join a team delivering verification closure across complex SoC projects. Applicants should have proficiency in SVTB/UVM, debugging, and scripting (Make/Perl/Python).
We are seeking a motivated Senior SV Verification Engineer (UVM/C++) to join Arrow Electronics in United States.
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
Learn more about the Senior SV Verification Engineer (UVM/C++) role in the description above.
We appreciate your interest in this position.
Join Arrow Electronics and contribute to our ongoing work.
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