DFT Engineering Director ASICS Engineering Posted

## DFT Engineering Director San Diego, California, United States of America Apply Now Find out how well you match with this jobJob :
3097028##
** Company:
** Qualcomm Technologies, Inc.##
** Job Area:
** Engineering Group, Engineering Group  ASICS Engineering
** General

Summary:

** As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.

The Digital ASIC Design Team is currently seeking candidates who will be responsible for the implementation and verification of advanced DFT/DFD (Design for Test/Design for Debug) techniques for low power, multi voltage designs. The successful candidate will help in the deployment of DFT methodologies that reduce test cost, increase product quality, and enhance yield learning on leading edge process technologies. The candidate should have solid hands-on experience with industry standard DFT techniques such as scan and MBIST.
Job responsibilities include DFT pattern generation, coverage analysis and debug as well as running and debugging gate level simulations. The ideal candidate will have experience in both pre, and post-silicon in the DFT domain.

All Qualcomm employees are expected to actively support diversity on their teams, and in the Company.
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* Minimum Qualifications:

*
* • Bachelor's degree in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience.
OR  Master's degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, validation, integration, or related work experience.
OR  PhD in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
** Preferred Qualifications
*** 15+ years industry experience in the implementation and verification of advanced DFT/DFD (Design for Test/Design for Debug) techniques for low power and multi voltage domain designs. A strong fundamental knowledge of DFT is required
* Understanding of core-based test methodology and scan isolation.
* Knowledge of various fault models such as Stuck-at, Transition, Path Delay, Gate-Exhaustive, IDDQ, and Cell Aware.
* Knowledge in JTAG, Scan Compression, ATPG, Fault Simulation and at-speed testing.
* Experience with industry EDA ATPG and insertion tools.
* Experience in DFT implementation, Scan/ATPG, MBIST insertion/validation, coverage analysis.  Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disabili or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process.

Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).
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