Sr RF Electromagnetic; EM) Engineer

Qualcomm Technologies, Inc.

Engineering Group, Engineering Group >
Packaging Engineering

As a Qualcomm Package System Design and Technology Engineer, you will drive new advanced package technology development, concept design architecture analysis from package to system, new generation product package structure selection, package system design by multi-physics simulation analysis, multi-physics lab validation/correlation of package to system models, and the manufacturing qualification for new product introduction (NPI). Package System Design and Technology Engineers collaborate with multi-disciplinary teams to achieve optimized performance of mechanical, electrical, and thermal package systems for various end market applications.

This role interfaces with internal/external IP teams, industry standards, and vendors to set package to system design and technology specifications; enabling product designs to achieve high performance, high reliability, low cost, and easy to implement system with integrated component attaches for end customers.

• • Bachelor's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 2+ years of System/Package Design/Technology Engineering or related work experience.
• OR
• Master's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 1+ year of System/Package Design/Technology Engineering or related work experience.
• OR
• PhD in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field.

• • Master's Degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field.
• • 3+ years of System/Package Design/Technology Engineering or related work experience.

• • Applies Package System Design and Technology knowledge to drive package product design layout, design multi-physics optimizations, design verification (DV), design tool flow development and tape out of discrete package or Module/SiP for all forms of bare silicon products (single or multi-die).
• • Assists package to system cooling architecture through simulations; assists in silicon and package product tapeouts, ensuring the thermal package system meets targeted performance, quality reliability, and cost targets.
• • Performs package to system electrical analysis and simulations for digital IP, analog IP and external components; supports SIPI, analog and PDN solution development across SoC, substrate, interposer, components and system platforms; assists in package to system tapeout preparation to meet electrical performance, quality reliability, and cost goals.
• • Simulates package mechanical interactions to optimize design, materials, reliability, etc. and improve product development efficiency.
• • Performs empirical testing on materials and devices, characterize mechanical/electrical performance, and analyze board/system level interactions.
• • Develops and implements packaging technology solutions for various end market applications to meet performance and cost targets.
• • Develops (structure/process/material/DRM), evaluates, and qualifies next-generation substrate technologies used in semiconductor packaging.
• • Develops and integrates next-generation heterogeneous integration solutions, including substrate, bridge die and interposer 2.5D chiplet architectures.
• • Develops and optimizes 3D integration technologies, including die-to-wafer, die-to-die, and wafer-to-wafer stacking for STCO, enables high-density interconnects, and implements design rules to ensure reliable and high yield die stacking technology.
• • Collaborates with team members to accomplish goals while meeting…