SOC Level Physical Design Engineer, Annapurna Labs

Job Description:

Annapurna Labs is seeking an experienced ASIC Physical Design Engineer to join the Cloud-Scale Machine Learning Acceleration team. This role focuses on the design and optimization of hardware for AWS Machine Learning servers, including custom chips and accelerators. The engineer will play a crucial role in ensuring high design quality and making informed trade-offs while working with cutting-edge technologies.

Responsibilities:

• Drive full chip floorplan, placement, integration, PV signoff, and tapeout.
• Collaborate with the Front-End team to understand RTL and influence physical aspects early in the design cycle.
• Define, execute, and optimize next-generation physical verification and integration methodologies using industry-standard EDA tools.
• Perform DRC, LVS, and PERC verification.
• Debug and resolve physical verification issues in collaboration with layout and design teams.
• Interface with foundries for MT form, rule deck updates, and violation waivers; develop and maintain verification runsets and methodologies.
• Mentor junior engineers on physical verification methodologies and closure.

Qualifications:

• BS in Electrical Engineering/Computer Science or related field with 10 years of experience, or MS with 7 years of experience.
• 5 years of experience in physical verification for advanced technology nodes.
• Proven track record of successful tape-outs.

Skills:

• Experience scripting with Python, Perl, Bash, or Power Shell.
• Expert knowledge of industry-standard physical verification tools (Calibre, IC Validator, PVS).
• Strong understanding of semiconductor manufacturing processes and design rules.
• Design Flow Knowledge:
  Understanding of backend physical design flows for chip-top/subsystems.

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

Free No obligation Response within 24 hours