Principal Design Verification Engineer - AI Data Center Chips

Top-Level Design Verification Engineer – Datacenter AI Hardware

Acceler8 Talent is partnering with a well‑funded startup (>$100m Series A), backed by world‑class investors, to hire an experienced Top-Level Design Verification Engineer. This team is building the next‑generation compute platform for companies developing and running GenAI models. Led by ex‑Google engineers who were instrumental in the development of Google's AI capabilities, it's safe to say the team has skin in the game.

You’ll join a highly skilled engineering group at the forefront of silicon design, report into the CDO and own large portions of verification execution at subsystem and chip‑level of a huge, high‑performance data‑center chip.

$250,000 – $350,000 per year.

• Stock options

• Help define and refine verification methodologies that scale from individual blocks to subsystems, full-chip environments, and system‑level validation.
• Take ownership of verification activities at the subsystem and chip levels, developing test benches, test suites, and supporting infrastructure to achieve both functional and structural coverage goals.
• Lead the planning and execution of verification reviews, including test plan assessments, progress updates, and closure evaluations, ensuring readiness for key silicon milestones such as design freeze and tapeout.

• Proven end‑to‑end verification experience, taking designs from architectural or specification‑level definition all the way through to production silicon.
• Proficiency in System Verilog along with scripting and programming languages such as Python, C/C++, Bluespec, or similar tools used for verification and silicon modeling.
• Demonstrated use of modern verification frameworks including UVM and assertion‑based methods; strong skills in both formal and simulation‑based verification are essential.
• Experience developing reusable tests, drivers, and infrastructure that can transition seamlessly into silicon validation and post‑silicon debug workflows.
• Solid understanding of microarchitecture and design principles for high‑performance compute systems (CPUs, GPUs, accelerators), high‑speed interconnects, memory subsystems, and related components.
• Familiarity with emulation and FPGA prototyping environments is beneficial.
• Hands‑on involvement in silicon bring‑up and debug is considered a strong plus.

• Join a well‑funded, fast‑growing startup shaping the future of GenAI compute.
• Work alongside industry‑leading architects and engineers.
• Hybrid role based in Mountain View, CA (3 days on‑site).

Mid‑Senior level

Full‑time

Semiconductor Manufacturing, Computer Hardware Manufacturing, and Computers and Electronics Manufacturing

Mountain View, CA

• Medical insurance
• Vision insurance
• 401(k)