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Senior PCIe RTL Engineer; Gen Stock
Job in
San Francisco, San Francisco County, California, 94199, USA
Listed on 2026-01-01
Listing for:
Eridu
Full Time
position Listed on 2026-01-01
Job specializations:
-
Engineering
Systems Engineer, Hardware Engineer -
IT/Tech
Systems Engineer, Hardware Engineer
Job Description & How to Apply Below
A Silicon Valley hardware startup is looking for an RTL Engineer, PCIe. This mid-senior level position requires 15+ years of ASIC/SoC RTL design experience, focusing on PCIe microarchitecture and protocol logic. The role involves developing high-performance buffering and protocol engines, technical leadership, and collaboration across teams to ensure system-level performance. Candidates should have a strong background in PCIe protocols and design flows.
Join us to shape the future of AI infrastructure with groundbreaking technology.
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Position Requirements
10+ Years
work experience
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