More jobs:
Design Verification Engineer — SoC/IP; SystemVerilog/UVM
Job in
San Francisco, San Francisco County, California, 94199, USA
Listed on 2026-01-01
Listing for:
Apple Inc.
Full Time
position Listed on 2026-01-01
Job specializations:
-
Engineering
Systems Engineer, Electronics Engineer
Job Description & How to Apply Below
A leading technology company seeks a hardworking design verification engineer in San Francisco. This role includes developing test plans and methodologies to ensure bug-free silicon for cutting-edge products. Candidates should have a BS degree with at least 3 years of experience, strong knowledge in System Verilog and UVM, and a passion for innovation. A competitive salary package is offered, along with stock options, comprehensive benefits, and opportunities for career advancement.
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