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Senior Design Verification Engineer; SystemVerilog & UVM
Job in
San Francisco, San Francisco County, California, 94199, USA
Listed on 2026-01-01
Listing for:
Amazon
Full Time
position Listed on 2026-01-01
Job specializations:
-
Engineering
Systems Engineer, Electronics Engineer
Job Description & How to Apply Below
A leading tech company in San Francisco seeks a Design Verification Engineer to develop verification methodologies and plans, ensuring the functionality of complex hardware designs. You will work closely with various engineering teams and require a strong background in System Verilog, UVM, and debugging. Candidates should have a Bachelor's degree and at least 7 years of relevant experience. This is an opportunity to contribute to innovative technology in a collaborative environment.
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Position Requirements
10+ Years
work experience
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