RTL Engineer, PCIe

Eridu AI is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate training and inference for large-scale AI models. Today’s AI performance is frequently limited by system-level bottlenecks. Eridu AI delivers multiple industry-first innovations across semiconductors, software, and systems to unlock greater GPU utilization, reduce capital and power costs, and maximize data center efficiency. The company’s solutions and value proposition have been validated by several leading hyperscalers.

The company is led by a veteran team of Silicon Valley executives and engineers with decades of experience in state-of-the-art semiconductors, optics, software, and systems, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (World’s leading micro-LED company and developer of the first augmented reality contact lens).

• Provide technical leadership for PCIe microarchitecture and RTL execution, ensuring robust design and adherence to performance, power, and area goals.
• Develop high-performance PCIe buffering, schedulers, and protocol engines.
• Own RTL development, including coding, documentation, code reviews, lint/CDC readiness, and block-level debug.
• Collaborate with Verification to define test plans, PCIe VIP usage, coverage goals, and debug complex protocol behaviors.
• Collaborate with Physical Design for timing closure in synthesis and place-and-route.
• Support post-silicon PCIe bring-up and validation focused on protocol correctness, link behavior, and subsystem performance.
• Collaborate with system and chip architects to ensure PCIe subsystem behavior aligns with chip-level bandwidth, latency, and power objectives.
• Partner with Architecture, DV, and Physical Design teams to achieve power, performance, and timing closure targets.

• MSEE with 15+ years of ASIC/SoC RTL design experience.
• Proven success designing PCIe controller or PCIe protocol logic (Gen4/Gen5/Gen6).
• Deep knowledge of PCIe LTSSM, TLP/FLIT pipelines, flow control, ordering rules, error mechanisms, and performance tuning.
• Strong RTL design skills with experience in multi-clock domains, timing closure, datapath optimization, and hardware/firmware partitioning.
• Familiarity with Ser Des behavior (equalization, training sequences) as required for correct PCIe protocol implementation.
• Familiarity with full ASIC design flow (DFT, synthesis, timing, and physical implementation considerations).
• Excellent analytical, problem-solving, and communication skills, with the ability to drive cross-functional technical execution.

At Eridu AI, you’ll have the opportunity to shape the future of AI infrastructure, working with a world‑class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI networking solutions, transforming data center capabilities.

The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.

The pay range for this role is:

210, USD per year (San Francisco Bay Area)