Senior Digital IC Design Engineer—RTL to Post-Layout

A leading global semiconductor company in San Francisco is looking for an experienced engineer specialized in ASIC/IC design. The position involves designing optimized digital blocks while ensuring compliance with functional, cost, and power constraints. Candidates should have over 10 years of experience in the IC design flow and be proficient in Verilog RTL coding. The role offers a hybrid work model, providing the opportunity to collaborate with a diverse team and make impactful contributions in the semiconductor industry.
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