Design Verification Engineer, Lab

As a Design Verification (DV) Engineer, you will be part of an advanced architecture team that is exploring new hardware designs to improve our devices. In this role, you will be responsible for defining the verification methodology and implementing the corresponding test plan for advanced functional blocks. You will participate in the design verification and bring‑up of such blocks by writing relevant assertions, debugging code, test benches, test harnesses, and otherwise interacting with the extended team.

You will work closely with multi-disciplinary groups including Product Design, Audio Technology, Computer Vision, Hardware Engineering, and Software Engineering, to architect and implement complex functional block that enable development of world‑class hardware devices. In this role, you will:

• Design world‑class hardware and software
• Communicate and work with team members across multiple disciplines
• Deliver detailed test plans for verification of complex digital design blocks by working with design engineers and architects
• Create and enhance constrained‑random verification environments using System Verilog and UVM
• Identify and write all types of coverage measures for stimulus and corner‑cases.
• Debug tests with design engineers to deliver functionally correct design blocks.
• Close coverage measures to identify verification holes and to show progress towards tape‑out.
• Participate in test plan and coverage reviews
• Integrate 3rd party IPs/VIPs and transactors
• Perform IP/SOC bring‑up in simulation, emulation and prototyping environments

The ideal candidate should have experience with RTL development environments, fluency in modern hardware description languages and verification methodologies. They should have experience verifying complex IP blocks from scratch that have successfully been integrated in SOCs or other such silicon that have been productized in consumer devices. We are looking for a self‑driven individual who can work with architects, HW and SW developers and can quickly resolve blocking issues.

• Bachelor’s degree or higher in EE, CE, or CS
• 7+ years or more of practical semiconductor design verification including System Verilog, UVM, assertions and coverage driven verification.
• Experience using multiple verification platforms: simulation, emulation or prototyping environments.
• Experience defining verification methodologies
• Experience with test plan development, test bench infrastructure, developing tests and verifying the design
• Experience with writing directed/constrained‑random tests
• Experience identifying bugs in architecture, functionality and performance with strong overall debug skills
• Experience verifying at multiple levels of logic from IP to SoC
• Experience with industry standard tools and scripting languages (Python or Perl) for automation
• Excellent verbal and written communication skills

• MS in Computer Science, Electrical Engineering, or related field.
• Experience with boot‑up and bare metal flows for CPU cores
• Experience with PCIE
• Experience debugging system‑level issues
• Strong programming skills in C and scripting skills in Python and/or Perl
• Experience with high performance industry standard IO interfaces like AMBA AXI4, USB, MIPI etc.
• Experience with PCIE
• Experience with formal verification
• Experience with transactors
• Experience with transaction level modeling
• Knowledge of FPGA and emulation platforms
• Knowledge of SoC architecture

Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit (Use the "Apply for this Job" box below). for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.

Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.