DFT Engineer - SoC​/ASIC Test & Validation

Match Point in San Francisco is seeking a DFT Engineer to define and execute robust Design-for-Test strategies for high-performance SoCs/ASICs. You will collaborate with front-end design, verification, and product engineering to ensure high test coverage and streamlined manufacturing test enablement.

The role covers pre-silicon execution, memory test, and post-silicon bring-up, with hands-on work in scan insertion, MBIST, JTAG, and ATPG, and interactions with PTE teams to optimize test time and

Are you ready to take on the DFT Engineer
- SoC/ASIC Test & Validation role at Match Point?

This role, DFT Engineer
- SoC/ASIC Test & Validation at Match Point, could be your next move.

We would love to welcome a new DFT Engineer
- SoC/ASIC Test & Validation to our organisation in San Francisco, CA, United States.

For the DFT Engineer
- SoC/ASIC Test & Validation position at Match Point, we are reviewing applications now.