Vivado FPGA Design Engineer - RTL & Timing Expert
Listed on 2026-10-11
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Engineering
Hardware Engineer, Systems Engineer, Electronics Engineer
Obsidian is seeking professionals with hands-on FPGA/RTL design experience. The role requires you to work with Vivado on Windows and to perform design tasks using real hardware.
We do not provide software licenses or hardware; candidates must supply their own Vivado setup and be ready to deliver artifacts and timing debugging. This position is based in San Francisco, California, with on-site work expected.
Step into the Vivado FPGA Design Engineer - RTL & Timing Expert role at Mercor in San Francisco, CA, United States and grow with us.
This opportunity is part of our work in Engineering.
The advertised compensation is 120..
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
Learn more about the Vivado FPGA Design Engineer - RTL & Timing Expert role in the description above.
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