Senior ASIC Validation Engineer – Post-Silicon Chiplet/UCIe
Listed on 2026-10-13
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Engineering
Test Engineer, Validation Engineer, Hardware Engineer
Eridu, a Silicon Valley hardware startup, is hiring a Post-Silicon ASIC Validation Engineer to lead bring-up and validation of multi-die networking SoCs and chiplet platforms. You will own validation planning, define coverage, and drive test execution across high-speed interconnects like UCIe, Ser Des, PCIe, and Ethernet PHYs in collaboration with architecture, design, firmware, and system teams.
This role offers opportunities to shape next-generation networking SoCs, develop automation, and
We are seeking a motivated Senior ASIC Validation Engineer – Post-Silicon Chiplet/UCIe to join Eridu in San Francisco, CA, United States.
Learn more about the Senior ASIC Validation Engineer – Post-Silicon Chiplet/UCIe role in the description above.
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