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Hybrid: Design Verification Engineer — AI Silicon & HPC

Job in San Francisco, San Francisco County, California, 94199, USA
Listing for: Acceler8 Talent
Full Time position
Listed on 2026-10-15
Job specializations:
  • Engineering
    Test Engineer, Validation Engineer, Systems Engineer, Hardware Engineer
Salary/Wage Range or Industry Benchmark: 120000 - 180000 USD Yearly USD 120000.00 180000.00 YEAR
Job Description & How to Apply Below

Acceler8 Talent is seeking an experienced Design Verification Engineer to advance verification across blocks to system-level validation for high-performance silicon. You will own verification in subsystems and full-chip contexts, building robust test benches and driving closures toward silicon milestones, in a hybrid SF Bay Area role.

Ideal candidates bring 5+ years in design verification, with knowledge of LPDDR/HBM and production experience with modern methodologies such as UVM, AVB, and formal

This posting is for the Hybrid:
Design Verification Engineer — AI Silicon & HPC role at Acceler8 Talent, based in San Francisco, CA, United States.

The Hybrid:
Design Verification Engineer — AI Silicon & HPC role at Acceler8 Talent is now open for applications in San Francisco, CA, United States.

Join us at Acceler8 Talent as our next Hybrid:
Design Verification Engineer — AI Silicon & HPC in San Francisco, CA, United States.

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