Digital Implementation Engineer

Digital Implementation Engineer — Snowcap Compute About Team FAQ Contact Design Jacksonville  Metro, FL / San Francisco Bay Area
· On-site

Now Hiring# Digital Implementation Engineer Synthesized netlist in. Tape-out-ready GDSII out. You will own the physical realization of Snowcap's superconducting digital chips — floorplan, placement, CTS, routing, power, and timing closure — on a non-CMOS PDK with no standard-cell autopilot to lean on.

Team Physical Implementation Employment Full -time

Posted

May 2026

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About the Role The chip program runs the standard sequence — architecture, microarchitecture, RTL, verification, implementation, sign-off — and implementation is where the design becomes physically realizable or it does not. The wrinkle at Snowcap is the PDK: superconducting logic, no decades of CMOS standard-cell history, and timing assumptions that the place-and-route tool was not written to assume. This is not a standard-cell autopilot job.  

You will own the digital implementation flow end to end: synthesis through floor planning, placement, clock tree synthesis, routing, power grid design and IR analysis, and timing closure to tape-out-ready GDSII. You will work directly with RTL design, design verification, and the sign-off engineer in a flat, matrixed organization. When the tool flow does not have the script you need, you will write it.

When timing will not close the way the textbook says it should, you will figure out which assumption failed and produce the flow that does close.  In twelve months, the implementation flow you stand up should be the one every block routes through and the one every sign-off engineer trusts the inputs from. The scripts, recipes, and methodology you write become the baseline every future implementation engineer at Snowcap inherits.
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What You'll Own
- Own the physical implementation of digital logic from synthesized netlist through tape-out-ready GDSII — every step, every tool stage, every closure decision.  - Drive floor planning, placement, clock tree synthesis, and routing on a non-CMOS PDK where the standard-cell shortcuts do not apply by default.  - Close timing — setup, hold, and the complex multi-corner cases — and diagnose where violations actually come from, not just where the report points.  

- Design and verify the power grid and run IR drop analysis appropriate to a superconducting current distribution that does not behave like CMOS.  - Drive DRC and LVS clean-up and the physical verification flow through to clean tape-out conditions.  - Partner with the Sign-off Engineer on final extraction, parasitic data, and the signoff checks that gate tape-out.  - Build and own the implementation flow itself: TCL, Python, recipe management, and the automation that turns a one-off block run into a repeatable production flow.  

- Set the implementation methodology and QoR standards at Snowcap — what a clean place-and-route database looks like, what closure means here, and what the next implementation engineer inherits.
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What We Need to See
- Track record of running the full digital implementation flow on production silicon — chips that you took from netlist to GDSII and that taped out and ran.  - Working fluency with Synopsys ICC2, Cadence Innovus, or equivalent production place-and-route platforms. Not a tool-evaluation level. Production level.  - Strong timing closure skills: setup and hold debug at scale, multi-corner multi-mode analysis, and the judgment to choose between RTL changes, floorplan changes, and CTS changes when a path will not close.  

- Solid working knowledge of power grid design, IR drop analysis, and the implementation decisions that determine sign-off outcomes downstream.  - Comfort with custom and…