Digital Sign-off Engineer

Digital Sign-off Engineer — Snowcap Compute About Team FAQ Contact Design Jacksonville  Metro, FL / San Francisco Bay Area
· On-site

Now Hiring# Digital Sign-off Engineer Sign-off is the last conversation a chip has before it goes to the mask shop. You will own that conversation — post-layout STA, parasitic extraction, DRC, LVS, power integrity, and the judgment call on what is a blocker, what is a waiver, and what is ready for fab.

Team Physical Implementation Employment Full -time

Posted

May 2026

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01

About the Role The chip program ends at sign-off, and sign-off is the last technical line of defense before a wafer is committed. The implementation team produces a design; this role decides whether that design is actually ready for fab. At Snowcap that decision is harder than at a CMOS shop — the PDK is non-standard, the rule decks are younger, and the extraction and timing assumptions that work at 7 nm CMOS do not transfer.

You will own the full sign-off flow: parasitic extraction, post-layout STA across corners, DRC, LVS, ERC, antenna, power integrity, EM, and the sign-off checklist that gates tape-out. You will work directly with the Implementation Engineer, RTL design, and the physics and fab teams in a flat, matrixed organization. You will be the engineer with the authority — and the obligation — to say "not yet" on a tape-out when the data does not support it, and to say "yes, this is the right waiver" when it does.

In twelve months, the sign-off methodology and checklists you stand up should be the artifact every tape-out decision at Snowcap runs through. The waiver discipline, the corner coverage, and the risk communication you establish become the standard every future sign-off engineer here inherits.
02

What You'll Own
- Own the final physical and electrical verification of completed layouts against the full set of design requirements — every check, every corner, every signed-off.

- Drive parasitic extraction and post-layout static timing analysis — set up the corners, interpret the results, and translate timing reports into actionable feedback for the implementation team.

- Execute and close DRC, LVS, ERC, and antenna checks against the foundry rule decks — including the judgment calls on what to fix versus what to waive.

- Drive power integrity, IR drop, and electromigration analysis appropriate to a superconducting current distribution that does not behave like CMOS.

- Own the sign-off checklist and the gating decision for tape-out — produce the evidence package, defend it under review, and be the engineer whose name is on "ready for fab".

- Communicate sign-off status and risk to the broader chip team in terms that architects, RTL, implementation, and physics can all act on.

- Author and maintain the sign-off methodology, scripts, and constraint files at Snowcap — including STA constraint development from scratch where the design has no inherited SDC.

- Partner with implementation on ECO planning when a sign-off finding requires a real fix late in the cycle.
03

What We Need to See
- Deep, production-level expertise with sign-off EDA tools — Calibre, Pegasus, StarRC, Prime Time, Voltus, or equivalent — on chips that taped out and ran.

- Track record closing tape-out on production silicon as the sign-off engineer of record, not as an adjacent contributor.

- Strong post-layout STA skills: multi-mode multi-corner, constraint development from scratch, and the judgment to know which violations are real and which are constraint problems.

- Working fluency with foundry rule decks and the discipline around DRC waivers — when a waiver is legitimate, when it is hiding a real problem, and how to document either way.

- Solid working knowledge of power integrity, IR drop, and…