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Research Engineer, Chip Design RL Reinforcement Learning

Job in San Francisco, San Francisco County, California, 94199, USA
Listing for: Anysilicon
Full Time position
Listed on 2026-10-18
Job specializations:
  • Engineering
    Systems Engineer, AI Engineer (Applied/Software)
Salary/Wage Range or Industry Benchmark: 180000 - 240000 USD Yearly USD 180000.00 240000.00 YEAR
Job Description & How to Apply Below
Position: Research Engineer, Chip Design RL [Reinforcement Learning]

Anthropic, San Francisco, CA Hybrid work

Job Description:

Anthropic is dedicated to creating reliable, interpretable, and steerable AI systems that are safe and beneficial for users and society. The company is expanding its team of researchers, engineers, policy experts, and business leaders to advance AI technology. The Reinforcement Learning (RL) teams play a crucial role in this mission, contributing to the development of Claude models and focusing on areas such as effective computer usage, code generation, RL research for large language models, scalable infrastructure, and enhanced reasoning capabilities.

The Code RL team is specifically looking for a Research Engineer to improve models' abilities in hardware design, particularly in silicon design.

Responsibilities:

  • Invent, design, and implement RL environments for RTL generation and verification.
  • Work on EDA-tool latency optimization and proxy rewards.
  • Conduct experiments and shape the research roadmap.
  • Deliver work into research and production training runs.
  • Collaborate with researchers and engineers across Anthropic.

Qualifications:

  • Expertise in ASIC or FPGA design, including RTL and design verification.
  • Fluency with industry EDA tools and processes.
  • Experience in chip design from specification to silicon.
  • Ability to balance research exploration with engineering implementation.
  • Passion for AI and commitment to developing safe systems.

Skills:

  • Experience with reinforcement learning and evaluations.
  • Familiarity with chip design automation tools.
  • Background in ML accelerators or high-performance compute hardware.
  • Knowledge of high-level synthesis or architecture simulators.
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