VLSI Design Engineer – Timing & P&R Expert
Listed on 2026-11-05
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Engineering
Engineering Design & Technologists, Electronics Engineer, Systems Engineer
TSMC Technology, Inc. in San Jose, California is seeking a Design Engineer to address DRC/LVS/EMIR issues, optimize floor plans and timing ECOs for high-performance blocks.
The role involves clock tree customization, floorplan, place and route, and signoff responsibilities. The candidate should hold a Master’s degree in Electrical or Computer Engineering, with strong experience in RTL coding, digital design, and state‑of‑the‑art EDA flows such as Cadence Innovus and Virtuoso.
The VLSI Design Engineer – Timing & P&R Expert role at TSMC is now open for applications in CA, United States.
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The position is based in CA, United States.
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